ChipSandbox
A browser-based RISC-V SoC playground that lets students and self-learners simulate the textbook's example designs without buying an FPGA board, with side-by-side waveform and RTL views.
Self-taught hardware engineers and EE students without access to lab FPGA boards
- Preloaded reference designs pulled from the Harris book's chapters, runnable in-browser
- Waveform viewer synced to the RTL source line that produced each signal
- One-click 'what happens if I change this bit width?' experiments with predicted performance impact
- Shareable lab links that instructors can drop into a class LMS
The RISC-V SoC textbook trend reflects a fast-growing community of students and hobbyists who can't afford $200+ FPGA dev boards to follow along with each chapter.
Real but moderate demand: Harris/Stine 'RISC-V System-on-Chip Design' (Elsevier, 2024/25) is a genuine textbook and the HN thread hit 64 points, but multiple free browser RISC-V/HDL tools (StudyRISC-V, CPUlator, EDA Playground, Wokwi) already serve this audience.RISC-V System-on-Chip Design - 1st Edition | Elsevier Shop ↗RISC-V Simulator with Step Execution | StudyRISC-V ↗
Crowded space: EDA Playground has a dedicated RISC-V playground, CPUlator supports RV32, StudyRISC-V, riscv.vercel.app, Velxio, and Wokwi all already offer browser-based RISC-V/HDL simulation; nothing in the existing tools is narrowly tied to the textbook chapters though.RISCV - EDA Playground ↗CPUlator Computer System Simulator ↗Wokwi Viewer (alpha) ↗
Weak WTP: EDA Playground is free, EasyEDA pitches itself as 'absolutely free' with only 'a few dollars' annual option, and the audience is students/hobbyists who already resist paying for FPGA boards; pricing pages of similar tools emphasize free tiers.Plans and Pricing - EasyEDA ↗Edit code - EDA Playground ↗
RISC-V momentum and the textbook give multi-year tailwind, but the niche education/EDA market commoditizes quickly (open-source iverilog, Verilator, Spike) so long-term defensibility is modest.RISC-V System-on-Chip Design Textbook and Course American Society for Engineering Education ↗
Reasonably buildable: iverilog/Verilator compile to WASM for HDL sim, Spike/emulators handle RISC-V ISA, and reference RTL ships with the textbook; main effort is the side-by-side waveform/RTL UI and per-chapter content curation.From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs - MDPI ↗3 EDA Playgrounds: Free Online RTL Simulators & Waveform Editor ↗